<html>
<head>
<link rel="shortcut icon" href="./favicon.ico">
<link rel="stylesheet" type="text/css" href="./style.css">
<link rel="canonical" href="./Address_Decoder_Behavioural.html">
<meta name="viewport" content="width=device-width, initial-scale=1">
<meta name="description" content="A programmable address decoder. Works for any address range at any starting point, *and the base and bound addresses can be changed at runtime*.  We express this behaviourally with two unsigned integer comparisons to check if the address lies between the base and bound of a range, inclusively.">
<title>Address Decoder Behavioural</title>
</head>
<body>

<p class="inline bordered"><b><a href="./Address_Decoder_Behavioural.v">Source</a></b></p>
<p class="inline bordered"><b><a href="./legal.html">License</a></b></p>
<p class="inline bordered"><b><a href="./index.html">Index</a></b></p>

<h1>Address Decoder (Behavioural)</h1>
<p>A programmable address decoder. Works for any address range at any starting
 point, <em>and the base and bound addresses can be changed at runtime</em>.  We
 express this behaviourally with two unsigned integer comparisons to check
 if the address lies between the base and bound of a range, inclusively.</p>
<p>This decoder scales to larger address ranges (20 bits or more) without
 hitting any Verilog implementation vector width limits or requiring long
 optimization of enormous netlists, as with the <a href="./Address_Decoder_Static.html">Static Address
 Decoder</a>.</p>
<p>How this circuit synthesizes depends on your CAD tool. In the past, I saw
 this code synthesize to the expected arithmetic comparisons via
 subtraction, but a more recent version of the same CAD tool synthesizes to
 log<sub>2</sub>(ADDR_WIDTH) levels of LUT logic. <em>But it is unclear if that
 will be faster than arithmetic circuitry.</em> And of course, if you make the
 base and bound addresses constant, the logic will optimize further towards
 its minimal form.</p>
<p>The base, bound, and input addresses all use the same width, which avoids
 the need for selecting parts of vectors and makes the enclosing code
 cleaner and more general.</p>
<p><strong>This is the implementation I recommend for general use.</strong> You can force
 a non-arithmetic implementation (but with a fixed range) by using the
 Static Address Decoder, or conversely, you can force an arithmetic
 implementation by using the <a href="./Address_Decoder_Arithmetic.html">Arithmetic Address
 Decoder</a>.</p>

<pre>
`default_nettype none

module <a href="./Address_Decoder_Behavioural.html">Address_Decoder_Behavioural</a>
#(
    parameter       ADDR_WIDTH          = 0
)
(
    input   wire    [ADDR_WIDTH-1:0]    base_addr,
    input   wire    [ADDR_WIDTH-1:0]    bound_addr,
    input   wire    [ADDR_WIDTH-1:0]    addr,
    output  reg                         hit
);

    initial begin
        hit = 1'b0;
    end

    reg base_or_higher = 1'b0;
    reg bound_or_lower = 1'b0;

    always @(*) begin
        base_or_higher = (addr >= base_addr);
        bound_or_lower = (addr <= bound_addr);
        hit            = (base_or_higher == 1'b1) && (bound_or_lower == 1'b1);
    end

endmodule
</pre>

<hr>
<p><a href="./index.html">Back to FPGA Design Elements</a>
<center><a href="https://fpgacpu.ca/">fpgacpu.ca</a></center>
</body>
</html>

